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Specifications

Warning

Unless otherwise stated, all specifications apply after 30 minutes of instrument warm-up.

Warning

Important changes in the specification parameters are explicitly noted in the revision history of this document.

General Specifications

Table 1: General and storage
Parameter min typ max
storage temperature –25 °C 65 °C
storage relative humidity (non-condensing) 95%
operating temperature 5 °C 40 °C
operating relative humidity (non-condensing) 90%
specification temperature 18 °C 28 °C
power consumption 60 W
operating environment IEC61010, indoor location, installation category II, pollution degree 2    
operating altitude up to 2000 meters    
power supply AC line 110–120/220–240 V, 50/60 Hz    
power supply Japan requires external 100 V to 110 V transformer (50/60 Hz) for operation according to specification    
dimensions with handles and feet 45 x 34 x 10 cm, 17.7 x 13.6 x 4.0 inch, 19 inch rack compatible    
weight 6.2 kg    
recommended calibration interval 2 years    
Table 2: Maximum ratings
Parameter min typ max
damage threshold HF inputs (Input 1, Input 2) –5 V 5 V
damage threshold HF outputs (Output 1, Output 2) –12 V 12 V
damage threshold Add inputs (Add 1, Add 2) –12 V 12 V
damage threshold Sync output (Sync 1, Sync 2) –12 V 12 V
damage threshold auxiliary outputs –12 V 12 V
damage threshold auxiliary inputs –12 V 12 V
damage threshold digital I/O (including DIO 0 and DIO 1 BNC connectors) 0 V 5 V
damage threshold Clock input 0 V 5 V
Table 3: Host system requirements
Parameter Description
supported Windows operating systems Windows 10, 11 on x86-64
supported macOS operating systems macOS 10.11+ on x86-64 and ARMv8
supported Linux distributions GNU/Linux (Ubuntu 14.04+, CentOS 7+, Debian 8+) on x86-64 and ARMv8
supported processors x86-64 (Intel, AMD), ARMv8 (e.g., Raspberry Pi 4 and newer, Apple M-series)
Table 4: Maximum sample readout rate
Active demodulators Maximum sample readout rate Comments
1 460 kSamples/s To achieve highest rates, it is advised to remove all other data transfer that loads the USB. It is recommended to check the sample loss flag (in the status tab) from time to time when using high readout rate settings.
2 – 3 230 kSamples/s  
4 – 6 115 kSamples/s  
7 – 8 57 kSamples/s  

Note

The sample readout rate is the rate at which demodulated samples are transferred from the Instrument to the host computer. This rate has to be set to at least 2 times the signal bandwidth of the related demodulator in order to satisfy the Nyquist sampling theorem. As the total rate is limited by the USB interface, the maximum rate becomes smaller when the number of active demodulators is increased. This is summarized in the table above for HF2LI / HF2PLL (6 demodulators) and HF2IS (8 demodulators). An up-to-date and performing host computer is required to achieve these rates.

Analog Interface Specifications

Table 5: HF signal inputs
Parameter min typ max
connectors front-panel single-ended/differential BNC    
input impedance (low value) 50 Ω
input impedance (high value) 500 kΩ 1 MΩ
input frequency range 0.7 μHz 50 MHz
input A/D conversion 14 bit, 210 MSamples/s    
input noise amplitude (> 10 kHz, AC coupling, 50 Ω and 1 MΩ), for detailed information see Figure 5 5 nV/√Hz
input amplitude accuracy (5 MHz), for detailed information see Figure 10 5%
input amplitude accuracy (10 MHz), for detailed information see Figure 10 10%
input amplitude stability 0.2 %/°C
input DC offset (<1 V input range) 20 mV
input DC offset (>1 V input range) 2%
input bias current – note: the bias current can lead to a DC offset voltage with input impedance high 100 nA 6 μA
input range settings 1 mV 1.5 V
input full range sensitivity (10 V lock-in amplifier output) 1 nV 1.5 V
input range (AC) with AC coupling –0.6 V 0.6 V
input range (AC) with DC coupling –1.5 V 1.5 V
input range (common mode) –3.0 V 3.0 V
input range (AC + common mode) –3.3 V 3.3 V
dynamic reserve 100 dB 120 dB
common mode rejection (CMRR), for detailed information see Figure 9 75 dB
AC coupling cutoff frequency 1 kHz -
Table 6: Reference
Parameter min typ max
internal reference frequency rangeInternal reference 0.7 μHz 100 MHz
internal reference frequency resolution 0.7 μHz
internal reference phase range –180 ° 180 °
internal reference phase resolution 0.1 μ°
internal reference acquisition time (lock time) instantaneous    
internal reference orthogonality 0 °
external reference at Input 2/Ref, signal type arbitrary, active at rising edge    
external reference at Input 2/Ref, frequency rangeExternal reference 1 Hz 50 MHz
external reference at Input 2/Ref, amplitude – note: for low-swing input signals the gain should be set to full-swing range to achieve best performance 100 mV 1 V
external reference at Input 2/Ref, amplitude (using HF2LI-PLL option) – note: for low-swing input signals the gain should be set to full-swing range to achieve best performance 10 mV 1 V
external reference at Input 2/Ref, reference acquisition time (lock time) 100 reference cycles or 1.2 ms whatever is larger
external reference at DIO0/DIO 1, signal type digital TTL versus ground    
external reference at DIO0/DIO1, frequency range 1 Hz 2 MHz
external reference at DIO0/DIO1, high level 2.0 V 5 V
external reference at DIO0/DIO1, low level 0 V 0.8 V
external reference at DIO0/DIO1, reference acquisition time (lock time) 100 reference cycles or 1.2 ms whatever is larger
external reference at AUXIN1/AUXIN2, signal type sine or rectangular    
external reference at AUXIN1/AUXIN2, frequency range 1 Hz 20 kHz
external reference at AUXIN1/AUXIN2, amplitude 0.5 V 1 V
external reference at AUXIN1/AUXIN2, reference acquisition time (lock time) 100 reference cycles
auto reference at Input 1/Input 2, signal type AC signal with zero crossings, AC input setting    
auto reference at Input 1/Input 2, frequency range 1 Hz 50 MHz
auto reference at Input 1/Input 2, reference acquisition time (lock time) 100 reference cycles or 1.2 ms whatever is larger
Table 7: Demodulators
Parameter Description
demodulator number HF2IS: 4 dual-phase, 8 dual-phase with multi-frequency kit
  HF2LI: 6
  HF2PLL: 6
demodulator harmonic setting range 1 to 1023
demodulator filter time constant 0.8 μs to 580 s
demodulator filter slope / roll-off 6, 12, 18, 24, 30, 36, 42, 48 dB/oct, consisting of up to 8 cascaded critical damping filters
demodulator output resolution X, Y, R, THETA with 64-bit resolution
demodulator output rate (readout rate), for detailed specifications refer to on Aux outputs: 921 kSamples/s
  on USB to host PC: maximum cumulative 700 kSamples/s
demodulator measurement bandwidth 83 μHz to 200 kHz
demodulator harmonic rejection max –90 dB
demodulator sinc filter operating range 0.1 Hz to 10 kHz
Table 8: HF signal outputs
Parameter min typ max
connectors front-panel single-ended BNC    
output impedance (Out and Sync) 50 Ω    
input impedance (Add) 1 MΩ    
output frequency range DC 50 MHz
output frequency range with 10 V amplitude. see also Figure 11 DC 5 MHz
output D/A conversion 16 bit, 210 MSamples/s    
output amplitude ranges (restrictions apply for high amplitudes and high frequencies, see Figure 11) ±10 mV, ±100 mV, ±1 V, ±10 V    
output maximum current 100 mA
output amplitude accuracy @ 3 MHz, < 5 V (restrictions apply for high amplitudes and high frequencies, see Figure 11) 1%
output total harmonic distortion THD (1 V, < 10 MHz), see Figure 12 –50 dB
output total harmonic distortion THD (0.1 V, < 10 MHz), see Figure 12 –60 dB
output noise amplitude (frequencies > 10 kHz), 50 Ω termination 25 nV/√Hz
output phase noise @ 10 MHz, BW = 0.67 Hz, offset 100 Hz –100 dBc/Hz
output phase noise @ 10 MHz, BW = 0.67 Hz, offset 1 kHz –120 dBc/Hz
output offset amplitude (range setting < 1 V) 10 mV
output offset amplitude (range setting > 1 V) 200 mV
input Add signal range –10 V +10 V
input Add signal bandwidth DC 50 MHz
output Sync signal range (effective range = ±1 * set_amplitude / set_range) –1 V 1 V
output synchronization signal resolution 30 μV
Table 9: Auxiliary Inputs and Outputs
Parameter Description
auxiliary output connectors front-panel single-ended BNC
auxiliary output impedance 50 Ω
auxiliary output number and type of signals 4, amplitude, phase, frequency, X/Y, manual
auxiliary output specification ± 10 V, 200 kHz, 16-bit, 921 kSamples/s
auxiliary output resolution 0.3 mV
auxiliary input connectors back-panel single-ended BNC
auxiliary input impedance 1 MΩ
auxiliary input number 2
auxiliary input specification ± 10 V, 100 kHz4, 16-bit, 400 kSamples/s
auxiliary input resolution 0.3 mV
group delay (lag time from HF input to auxiliary output) 7 μs (typical), 10 μs (maximum)
Table 10: Oscillator and clocks
Parameter min typ max
internal oscillator frequency 10 MHz
internal oscillator output (sine) –1 V +1 V
internal oscillator initial accuracy (serial number HF2-DEV1141 and lower)1 ±30 ppm
internal oscillator aging (stability; serial number HF2-DEV1141 and lower)1 ±5 ppm/year
internal oscillator temperature stability (23 °C ± 5 °C; serial number HF2-DEV1141 and lower)1 ±30 ppm
internal oscillator initial accuracy (serial number HF2-DEV1142 and higher)2 ±1.5 ppm
internal oscillator temperature coefficient (23 °C ± 5 °C; serial number HF2-DEV1142 and higher)2 0.05 ppm/C
internal oscillator phase noise (at 100 Hz) –125 dBc/Hz
internal oscillator phase noise (at 1 kHz) –140 dBc/Hz
UHS (option) oscillator initial accuracy3 ±0.5 ppm
UHS (option) oscillator aging (stability)3 ±0.4 ppm/year
UHS (option) oscillator temperature stability (23 °C ± 5 °C)3 ±0.03 ppm
UHS (option) oscillator phase noise (at 100 Hz)3 –130 dBc/Hz
UHS (option) oscillator phase noise (at 1 kHz)3 –140 dBc/Hz
UHS (option) oscillator reference stability (over 30 s)3 0.00005 ppm
UHS (option) oscillator time to reach specification3 60 s
external clock connector back-panel single-ended BNC    
external clock input impedance 1 MΩ    
external clock input voltage 0 V +3.3 V
external clock frequency 9.98 MHz 10 MHz 10.02 MHz

Digital Interface Specifications

Table 11: Digital interfaces
Parameter Description
host computer connection USB 2.0 high-speed, 480 Mbit/s
ZCtrl pre-amplifier control bus proprietary bus to control external pre-amplifiers
ZSync synchronization bus proprietary bus to locally interconnect ZI instruments
DIO connector 32 bit, general purpose

The DIO connector is a HD 68 pin connector, typically also used by SCSI-2 and SCSI-3 interfaces, 47 mm wide male connector. The DIO port features 16 bits that can be configured byte-wise as inputs or outputs, as well as 16 input only bits. The digital signals follow the CMOS/TTL specification.

Figure 1: DIO HD 68 pin connector

Table 12: DIO pin assignment
Pin Name Description Range specification
68 CLKI clock input, used to latch signals at the digital input ports - can also be used to retrieve digital signals from the output port using an external sampling clock 5 V CMOS/TTL
67 DOL DIO output latch, 64 MHz clock signal, the digital outputs are synchronized to the falling edge of this signal 5 V CMOS
66–51 DI[31:16] digital input digital input CMOS/TTL level
50–35 DIO[15:0] digital input or output (set by user) output CMOS 5 V, input is CMOS/TTL
34–3 GND digital ground
2–1 PWR 5 V supply (100 mA max)

Figure 2: DIO input/output architecture

The HF2 Digital I/O Breakout Board provides an easy way to access all pins of the DIO Connector. The board consists of 68 pin headers and a 68-pin female socket to be connected to the HF2 using a ribbon cable. For description of the pins, refer to the Table 12. The HF2 DIO Breakout Board is available with Zurich Instruments on demand.

Figure 3: HF2 digital I/O breakout board

The internally generated 10 MHz clock is made available for external synchronization at the ZSync Out RJ45 connector. The clock signal is at pin 1, ground at pin 2. To connect: simply prepare a cable assembly that allows you to connect the 10 MHz signal from the HF2 to the BNC input of the other device external clock.

Figure 4: The pinout of the RJ45 jack

Performance Diagrams

Many parameters mentioned in Analog Interface Specifications are valid without specific conditions. Other parameters instead are typical specifications because they depend on several parameters, such as range settings, and frequency. This section completes the previous chapters with detailed performance diagrams in order to support the validation of applications.

Figure 5: HF input noise with AC coupling

Figure 6: HF input noise with DC coupling

Figure 7: HF input total harmonic distortion with AC coupling

Figure 8: HF input total harmonic distortion with DC coupling

Figure 9: HF input common mode rejection ratio

Figure 10: HF input bandwidth

Figure 11: HF output amplitude accuracy

Figure 12: HF output total harmonic distortion

Figure 13: HF output bandwidth

Figure 14: Lock time

Figure 15: HF2 signal output phase noise

Ground and Earth Scheme

Ground loops may introduce noise at the line frequency (mostly 50/60 Hz) and its harmonics, and aliasing in the demodulated signal that is measurable for frequencies up to 10 MHz. Some lock-in amplifiers implement a line filter which has the effect to exclude low frequency measurements. This is not the case for the HF2 Instruments where an effective ground strategy is implemented.

In order to suppress large signal components at line frequency and higher harmonics avoiding ground loops within the measurement setup is required. Possible reasons for line frequency components include parasitics resistances between the different signal grounds, inductive coupling from line transformers and other electrical apparatus into the signal paths, and pre-amplifiers that generate additional loops.

Counter measures are to break loops using differential wiring, by implementing star ground connections in the measurement setup, with the main ground closest to the setup as possible, connect all instrument casing to earth, and using optocouplers and transformers that provide a galvanic decoupling in the signal path.

The grounding of the HF2 Instrument is implemented connecting analog ground and digital ground in a star network. This reduces the digital ground noise that flows into the analog domain considerably. All analog grounds are connected together before they are connected to the digital ground (e.g. USB ground). All grounds are decoupled by the Earth by means of a 1 MΩ resistor, which is however generally shorted by a PC connected by means of a USB cable. The earth connection of the power plug connects at the same time the chassis and the banana plug on the rear Instrument panel.

Figure 16: Instrument ground and earth connection scheme

For applications that require floating ground, it is suggested to make use of the differential inputs by connecting the BNC shield to the negative BNC connector. The limitation for this strategy is that the floating ground should not exceed the specified maximum input common mode offset.

Figure 17: Differential connection scheme reducing ground loops

When using ZSync to synchronize two HF2 Instruments, the 10 MHz clock may couple into the signal path and disturb the lock-in measurement at certain frequencies. Below are two measures to counteract this potential problem.

  • Connect the Clock In connectors on the back panel of the instruments with a short BNC cable. This cable has the sole purpose of connecting the digital grounds of the instruments and has no effect on the 10 MHz clock.
  • Wind the Ethernet cable used to connect the ZSync ports into small coils and/or attach a ferrite bead to the cable.

Reference Images

The following figures are intended for advanced users with programming projects on the HF2 Instruments.

Figure 18: hf2is block diagram

Figure 19: hf2li block diagram

Figure 20: hf2limfk block diagram

Test Specifications

Users are encouraged to verify that the Instrument performs as specified, not only after shipping but also to ensure continuous performance over time. Recommended procedures for measuring key specification parameters are based on the Zurich Instruments ziControl software. For detailed instructions please refer to the Specifications chapter of the HF2 User Manual (ziControl Edition) available at https://www.zhinst.com/products/hf2li-lock-amplifier.